1. Field of the Invention
The present invention relates to a decoder circuit having small power consumption.
2. Description of the Prior Art
A decoder circuit, for decoding an address signal for selecting a memory cell of a memory circuit, selects one of a plurality of word lines of the memory circuit and one or two of its bit lines. Such a decoder circuit is usually comprised of a NOR gate. It is determined that a particular word line is selected or unselected in dependence upon whether the decoded output is a high-level or a low-level. When the low-level output is produced, a current flows from the power supply via the NOR gate to the ground side, causing power consumption.
With an increase in the capacity of the memory circuit, the number of word lines and bit lines increase and the scale of the decoder circuit becomes large because it is selecting among the large number of word lines and bit lines addressed by the address signal. For example, when one word line is selected leaving the other word lines unselected, a number of decoders yield the low-level outputs, resulting in a large current flow and causing the total power dissipation to become so large that it can not be considered negligible. Accordingly, it is necessary to reduce such power dissipation.
For example, a large capacity memory circuit is usually formed by packaging a plurality of memory cards, each memory card having mounted on its print board a plurality of LSI memory chips each of which has a large number of memory cells because each chip has a high density of components. When accessing the memory circuit, a chip select signal is used for selecting a desired one of the memory chips. It has been proposed to cut power consumption by connecting the power source only to the decoder circuit of the memory chip selected by the chip select signal.
For instance, FIG. 1 shows the principal part of a conventional decoder circuit, illustrating only the part corresponding to one word line. In FIG. 1, reference character Qa indicates a depletion type load MOS transistor; Qb designates an enhancement type MOS transistor for power cutting use; and Q.sub.0 to Q.sub.n identify MOS transistors comprising a NOR gate. The MOS transistors Q.sub.0 to Q.sub.n have their drains conected together to the source of the transistor Qb to receive a voltage signal and a word line WD and to have their sources grounded or connected to a low-potential point and are supplied at their gates with address signals A.sub.0 to A.sub.n, respectively. When a chip select signal .phi..sub.0 becomes the high-level, the MOS transistor Qb is turned ON and, in this case, if the MOS transistors Q.sub.0 to Q.sub.n forming the NOR gate are all in the OFF state, a power supply voltage V.sub.DD is applied via the MOS transistors Qa and Qb to the word line WD. In other words, when all bits of the address signals A.sub.0 to A.sub.n are the low-level, the word line WD becomes the high-level and is thus selected by the address signal.
When one or more bits of the address signals A.sub.0 to A.sub.n are high-level, the MOS transistors corresponding to the high-level bits are turned ON, by which the word line WD assumes the ground potential or the potential of the low-potential point; namely, the word line WD becomes low-level and therefore unselected. Assuming, for example, that only the address signal A.sub.1 becomes high-level, the MOS transistor Q.sub.1 is turned on and consequently the current supplied by the power supply voltage V.sub.DD flows via the MOS transistors Qa, Qb and Q.sub.1 to the ground side. In an unselected memory chip, however, since the chip select signal .phi..sub.0 becomes low-level, the MOS transistor Qb is turned OFF to cut off the current flowing through the NOR gate, thus reducing power dissipation.
With the inclusion of the MOS transistor Qb which is turned ON and OFF by the chip select signal .phi..sub.0, as described above, it is possible to cut the power dissipation of unselected memory chips, but this method poses such problems as mentioned below. Since the word line WD has connected thereto a number of static memory cells, each formed, for example, by a flip-flop, the stray capacitance of the word line WD is relatively large. When the word line WD is selected, it is necessary to charge its stray capacitance, so that the rise-up time of the word line WD becomes long. Further, in order that the word line WD, once charged, may be made unselected, charges stored in the word line WD must be discharged by making any one of the address signals A.sub.0 to A.sub.n the high-level to turn ON one or more of the MOS transistors Q.sub.0 to Q.sub.n forming the NOR gate. For rapid charging and discharging of the word line WD, it is necessary to employ large current capacity MOS transistors as the MOS transistors Qa, Qb and Q.sub.0 to Q.sub.n, but this creates the problems that a large current flows when the word line WD is unselected and that the stray capacitance of the MOS transistors Q.sub.0 to Q.sub.n forming the NOR gate becomes so large as to increase the load capacitance of the address signal line, resulting in the operating speed of the NOR gate being reduced.